Nobody puts advanced packaging on a keynote slide, yet it's the single most congested step in the AI chip supply chain. Chiplets let designers build enormous processors out of smaller, manufacturable pieces; CoWoS is what glues those pieces and their HBM stacks into one working unit. If the wafer is the brain, packaging is the nervous system — and right now, the nervous system is underbuilt.
Why monolithic dies hit the wall
A single huge GPU die runs into three brutal problems: yield (one defect kills the whole expensive die), reticle size limits (you can't print arbitrarily large patterns in one exposure) and cost (defect density scales against you as area grows). The industry's answer has been to stop fighting physics and start composing: break the big chip into smaller dies — compute dies, I/O dies, cache chiplets — and connect them in advanced packages. This is the chiplet era, and it's why AMD's EPYC, NVIDIA's Blackwell and a growing roster of AI ASICs are all multi-die designs under the hood.
Chiplets change the economics of leading-edge nodes too. You can put only the logic that needs N3 or N2 on the fancy node and move I/O and analog onto cheaper, mature nodes. That's real money saved per unit, and it's become standard practice rather than exotic engineering.
CoWoS, explained without the jargon
TSMC's Chip-on-Wafer-on-Substrate is the dominant advanced packaging platform for AI accelerators. The flow, simplified: build a silicon interposer (a big passive silicon slab with ultra-dense wiring), place the GPU chiplets and HBM stacks on it side by side, then mount the whole interposer onto an organic substrate that fans out to the rest of the system. The interposer's short, dense interconnects are what let the GPU and HBM talk at multi-terabyte-per-second rates.
CoWoS comes in flavors — CoWoS-S (interposer), CoWoS-R (RDL-based, cheaper), and newer variants pushing interposer size larger. The interposer itself is the hard part: large, defect-prone, and constrained by mask and lithography limits. A modern AI accelerator package might use an interposer approaching or exceeding reticle stitching territory, and every millimeter of interposer is yield you have to earn back.
Why packaging capacity keeps running out
TSMC has expanded CoWoS capacity aggressively for two years, reportedly targeting well over 100k wafers per month in the near term — up from roughly a third of that in 2023. And yet demand still outruns supply, because every Blackwell-class accelerator soaks up a huge interposer area. Allocations are effectively spoken for by NVIDIA and the big ASIC programs years in advance.
The consequences are concrete:
- Allocation, not wafer price, decides who ships AI chips and who waits.
- Lead times for CoWoS-based parts stretch into quarters; designers must lock packaging slots before tapeout.
- Second-source packaging (Amkor, ASE, Samsung's packaging line, Intel's EMIB/Foveros) is getting serious attention, though qualifying a new packaging partner for a flagship accelerator takes roughly a year or more.
The alternatives jostling for position
CoWoS is the incumbent, not the only path. Intel's EMIB (embedded multi-die interconnect bridge) avoids the giant interposer by embedding tiny bridges only where die-to-die links are needed — more elegant, arguably better yield economics at scale, and central to Intel's pitch with its own accelerators and external customers. Intel's Foveros 3D stacking goes the other direction, stacking dies vertically. TSMC has its own 3DCoWoS variants for vertically stacked logic and cache.
On the interconnect standards side, UCIe (Universal Chiplet Interconnect Express) is maturing as the cross-vendor die-to-die spec. It won't magically create capacity, but it lowers the friction of mixing dies from different vendors, which is where the whole industry wants to go: disaggregated silicon as a marketplace rather than a megaproject per chip.
What breaks if packaging stays scarce
Follow the knock-on effects. If CoWoS stays tight, accelerator supply stays flat, inference prices stay high, and every lab rations capacity — which pushes them toward whatever token-efficient tricks (sparsity, quantization, MoE routing) squeeze more output from fixed hardware. It also props up NVIDIA's pricing power, because whoever controls allocation controls the market. For challengers like AMD's Instinct line or Google's TPU, packaging throughput is the difference between a credible second source and a slide in a pitch deck.
There's a strategic angle too. Packaging concentration mirrors fab concentration: almost all leading-edge advanced packaging capacity sits in Taiwan, with growing but limited expansion into the US and Japan. Anyone who models AI supply chain risk correctly is modeling packaging geography, not just wafer geography.
The bill of materials nobody tweets about
Crack open a CoWoS package cost model and the interposer dominates. A large silicon interposer is printed on reticle-class lithography with several metal layers; at AI-accelerator sizes, one interposer can cost several hundred to several thousand dollars before a single transistor is placed on it. Then comes the organic ABF substrate — itself in chronic shortage for large, high-layer-count boards — then the chiplets, then the HBM, then assembly, test and burn-in. By the time a package passes final test, the value embedded in it rivals a mid-range car.
Assembly houses earn thin margins but hold enormous leverage right now, because requalifying a package flow takes months of joint engineering between the designer and the OSAT. This is why NVIDIA guards its packaging recipes closely and why competitors spend so much on process co-development with TSMC and Amkor rather than treating packaging as a commodity afterthought.
What the roadmap looks like from here
CoWoS isn't standing still. TSMC is scaling interposer sizes toward and beyond stitching limits, rolling out CoWoS-L (with local silicon interconnects replacing full interposers in some configurations) to cut cost and raise effective area. 3D stacking roadmaps promise logic-on-logic and cache-on-logic assemblies that multiply package density again. Panel-level packaging — building on large panels instead of round wafers — is the long-promised cost breakthrough, and pilots are progressing, though commercial ramp is years away.
For the impatient, the near-term relief valve is yield. Every point of yield improvement on twelve-layer HBM-bonded packages converts directly into thousands of additional accelerators per year. Yield engineering, not glamour, is where the next capacity surge will come from.
How hyperscalers are routing around the queue
When packaging slots run out, the big buyers get creative. Google designs its TPU with packaging co-optimization from day one, working directly with TSMC's advanced packaging engineering to lock capacity. Amazon runs Trainium through similar partnerships, and Microsoft's Maia program treats package design as a first-order constraint alongside die design. The pattern is consistent: whoever co-owns the packaging flow gets the allocation. That's a massive edge NVIDIA no longer enjoys unchallenged, because the hyperscalers now spend enough to earn a seat at the same table.
Smaller players respond with pragmatism. Some AI accelerator startups are exploring fan-out wafer-level packaging and even 2.5D alternatives that sacrifice peak bandwidth for availability. Performance per dollar suffers, but shipping matters more than winning benchmarks. A chip in a server beats a chip in a slide deck every single time.
Yield: the metric that decides everything
Advanced packages fail in new and creative ways: voids in die attach, delamination between interposer and substrate, micro-bump shorts after thermal cycling, and subtle warpage that only reveals itself weeks later. Each failure mode demands its own inspection regime — X-ray, acoustic microscopy, warpage metrology — and each escapes only as rarely as the process allows. The best packaging lines run first-pass yields in the high nineties by percent for mature parts, but brand-new package designs for flagship accelerators often limp along at 70-80% until the process matures. That ramp, not the announcement date, is what actually sets availability.
The substrate squeeze behind the scenes
Long before an interposer enters the picture, the large ABF (Ajinomoto build-up film) organic substrate has to be drilled, plated and laminated with tolerances measured in microns. Suppliers like Ibiden, Unimicron and Samsung Electro-Mechanics control much of this capacity, and the biggest, highest-layer-count boards for AI packages are chronically oversubscribed. Substrate lead times stretch for months, and a single warpage fault inside a laminate kills an assembly that already carries a fortune in silicon. When packaging people complain about “the whole chain,” the substrate layer is usually the one they mean.
The workforce problem inside the packaging line
Packaging is strangely labor-dependent for such high technology. Skilled process engineers, warpage metrologists and yield specialists take years to train, and there simply aren't enough of them. Every CoWoS expansion announcement sounds like concrete and equipment, but the real ramp limiter is hiring and retaining people who understand bonded-die stacking at micron tolerances. It's a niche so small that a handful of universities and a few fabs effectively own the talent pipeline — and that scarcity shows up as slower yield maturation for every new package design.
The IP and trust problem in disaggregated silicon
Once your chip is assembled from dies made by different vendors — maybe a compute die from one IP house, an I/O die from another, memory from a third — the question of who owns what gets uncomfortable. Known-good-die testing has to happen before assembly, because a single faulty chiplet ruins an entire package. That shifts testing discipline upstream into a place it was never designed to live, and it means chiplet vendors have to share yield and defect data under NDAs that lawyers are still sweating over.
Security follows a similar curve. UCIe links between dies can be probed or replayed if the physical interface isn't designed defensively, and side channels across die boundaries are genuinely hard to reason about. For an AI accelerator inside a hyperscaler, fine. For a chip going into defense or medical gear, die-to-die encryption and attestation are becoming real requirements, not slide-ware. The industry is slowly standardizing chiplet security, but today every serious multi-die design bakes its own trust model onto the package. Disaggregation isn't just a manufacturing shift; it's a contract-and-trust shift that the standards bodies haven't fully caught up with yet.
The bottom line
Chiplets solved the unbuildable-die problem and created the unbuildable-package problem. That's the trade, and it's a good one — yield and economics both favor disaggregation. But until CoWoS-class capacity catches up with demand, the packaging line is where AI ambition goes to queue. If you're betting on next year's accelerator market, count packaging slots, not FLOPS. The spreadsheet lives there.